1. Field of the Invention
This invention relates, in general, to reset circuits and more particularly to a reset circuit for data latches of a digital to analog converter.
2. Background Art
Digital to analog converters implemented with bipolar transistors typically have a plurality of differential transistor pairs functioning as switches. Digital input signals representative of a binary number determine the on-off state of each switch wherein the on state of each switch supplies a binary scaled bit current to a summing bus to form an analog signal corresponding to the digital input signal.
A typical switch, wherein the output may be latched, includes a first differential transistor pair biased by a digital input signal and an inverse digital input signal, a second differential transistor pair that are cross-coupled and are responsive to the output of the first pair, a third differential transistor pair responsive to the output of the first and second pair for directing an output current onto a summing bus, and a fourth differential transistor pair responsive to toggle and latch signals for enabling either the first or second pair. In order to reset the latch, a transistor is provided that diverts current to ground from the base of one of the cross-coupled pair that is biased on. As the voltage is pulled down below the voltage at the base of the other one of the cross-coupled pair, the cross-coupled pair invert their on-off state, thus, resetting the latchable switch. However this configuration consumes an undesirable amount of power in the reset mode and is difficult to match logic thresholds. Furthermore, the capacitive loading adds imbalance and the reset circuit is fast only if voltage driven.
Another known configuration for the reset portion of the switch has the transistor diverting the current to the collector of the fourth differential pair. However, as in the prior configuration, capacitive loading adds imbalance and it is difficult to match logic thresholds in all applications. Furthermore, this configuration requires hard saturation of the reset transistor.
Thus, what is needed is a reset circuit for data latches that has good speed, matched logic thresholds, low power consumption, and does not add imbalance to the latch.